1. Field of the Invention
The present invention relates to an improved phase lock loop system, and more particularly to a phase lock loop system for fast frequency switching radar or electronic counter measure systems.
2. Prior Art Discussion
In radar systems suitable for moving target indication, it is necessary that the generated pulses are precisely in a fixed phase relationship to a master oscillator in order that the phase shift of the received or echo pulses can be accurately detected for discriminating between moving and stationary targets.
In the past, such radar systems generated phase coherent pulses of a single selected frequency. However, such single frequency transmission could readily be rendered ineffective if other radar systems in the same area were generating pulses of the same frequency; such as would be the case, where there was intentional jamming, for example. Therefore, radar systems were built that had the ability to change frequencies automatically in the event that interference occurred on the frequency being used.
In a radar system with a 200 mile range, for example, the pulse repetition frequency is 330 Hz. Thus, the pulse echo for each respective pulse reaches the receiver in 2.46 milliseconds. It is the time between the reception of the pulse echo and the next pulse transmission that is left for changing frequencies. In the example given, this time for changing frequencies, which is termed "dead time" is in the order of 0.54 milliseconds. However, this dead time can be much shorter or longer, depending on range and pulse repetition frequency.
In advanced radar systems it is desirable to be able to change the receiving frequency rapidly and to be able to select as many frequencies as possible during the available dead time in order to perform a jamming analysis. Thus, it is necessary that such change must be effected rapidly in the order of 30 microseconds, for example.
In such radar systems, it is preferable to use what is commonly termed a "phase lock loop" for maintaining the generated frequency pulses in an exact phase relationship with a master oscillator, regardless of variations caused by temperature differentials or other drifts in the components. A typical prior art phase lock loop is shown schematically in FIG. 1, and includes a voltage controlled oscillator (VCO) 10 having a coarse tuning port 11 and a fine tuning port 12. The output of the VCO 10 is a frequency that depends on the value of the input voltages applied to the coarse and fine tuning ports 11 and 12. The coarse tuning voltage is supplied by an integrator 13. The input voltage to the VCO 10 from the integrator 13 remains constant when its input 14 has 0 volts. A reference frequency on 15 is compared with the output frequency on line 16 of the VCO 10 by a phase detector 17. At times when the output frequency of the VCO 10 changes its phase with respect to the reference voltage, a DC error voltage appears on line 18 at the input to an amplifier 19, the output of which is connected to a second amplifier 20, and the input 14 of the integrator 13. The amplified error voltage, which is applied to the coarse and fine tuning ports 11 and 12 varies the input voltage to the VCO 10 to correct the phase of the frequency from the VCO 10 to reduce the error voltage. Thus, the loop is self-correcting to maintain the proper phase relationship with the reference voltage. When the reference voltage frequency on line 15 is the same as the output frequency on line 16 with the loop operating in a manner to maintain the proper phase, the loop is in a "locked" condition. Thus, in locked condition, the fine tuning voltage is nearly zero and the coarse tuning voltage has a fixed value.
To change the frequency, the reference frequency on the line 15 is changed to the desired frequency and a switch 21 is closed momentarily to apply a "sweep" control voltage to the input of the integrator 13 for changing the input voltage to the VCO 10 such that loop can self-lock at the new frequency.
When the frequencies of the reference voltage and the VCO voltage differ, the loop is said to be "unlocked". In the unlocked condition, an alternating voltage appears at the output of the phase detector. If, by external means, the VCO tuning voltage is made to vary towards the new voltage, representing the new frequency, the phase lock loop will go to the locked condition. The two frequencies are equal, but their initial phase difference is still undergoing a change until, at the end of the so-called phase settling time, their phase relationship does not change any more. Thus, the loop goes through a settling period while the loop self-corrects to reduce the amplifier 20 phase error voltage to zero for the proper and final phase relationship. This phase settling time can be much longer than the time required for the frequency change alone. Therefore, in summary, for every change of frequency, the loop goes through two steps. The first step is a change of frequency, until the loop is "locked", but the phase has not yet stabilized. The time required for this step is referred to as the "capture" time. The second step is the time required for the phase of the loop to become stabilized. This step is referred to as the phase "settling" time.
It is well known that the greater the amplitude of the input voltage to the loop integrator 13, the faster that it will react to provide the desired change in voltage to the VCO 10. However, if the voltage is too great, the loop will go right through the proper value and will not "lock". If the amplitude is relatively low, the time required for the integrator to change its output voltage is too slow. Therefore, in order to insure that the loop "locks" in response to a change in frequency in the least amount of time, a "sweep" control voltage is provided upon the closure of the switch 21 (FIG. 1) which "pre-positions" the new voltage just short of the new required voltage as shown in FIG. 2. Assuming that the system is operating at frequency F1 and a change is to be made to frequency F2, the input voltage to the integrator 13 is changed to a voltage corresponding to the lower band limit rapidly; and is then rapidly reversed until it reaches a voltage represented as P, which is slightly less than the voltage required for the frequency F2, at which time the switch 21 opens. Due to the high rate of change of the tuning voltage, the loop cannot lock. Therefore, from point P on, the sweep rate must be reduced to allow the loop to lock at point Q. The maximum allowable sweep rate for self-locking depends on loop gain and loop bandwidth. At the capture point Q, the first portion of the transfer is complete and the "settling" time period begins, which is much longer than the capture time. The reason for this is the inherently slow integrator response. With reference to FIG. 3, it is seen that the loop can "lock" at any point within the "capture" range where an error voltage as represented by line 24 exists. At any point along line 24, with the exception of the precise point T.sub.O, the loop is locked, but not yet phase stabilized.
Assuming that the switch 21 (FIG. 1) opens at point P, for example, a slow sweep is initiated through switch 21' from P to Q of FIG. 2 until it self-locks, such as at point Q, for example, in the capture range. Thus, in such case, the settling time extends from time T.sub.1 to T.sub.0, which may be in the order ot one to ten milliseconds. The time T.sub.0 on line 24 corresponds to the precise voltage required for the proper phase relationship of the new frequency.
It follows that the "settling" time for the typical loop after a change in frequency can be anywhere along line 24 between X and Y. Thus, the closer that the point Q is to the time T.sub.0, the faster a transfer can occur from one frequency to another with a much shorter phase "settling"time.
U.S. Pat. No. 3,795,870 proposes a phase lock loop wherein means are proposed to increase the speed of locking of the loop by operating a frequency/phase detector circuit in the frequency detector mode when the loop is "unlocked"to control a speed-up circuit to slow the oscillator to the "lock" condition. While the speed-up circuit brings the loop to the locked condition, the bandwidth of the loop is at a high value to provide a fast loop response. When the loop is able to lock, the bandwidth is lowered to the optimum value for good noise performance. Although this patent directs itself to speeding up the locking, the system can still lock itself anywhere within the "capture range".
Therefore, it is desirable to provide a phase lock loop system that is controllably locked to thereby substantially reduce the phase settling time when transferring from one frequency to another.